Dual Phase Detector Based Delay Locked Loop for High Speed Applications

In this paper a new architecture for delay locked loops will be presented.  One of problems in phase-frequency detectors (PFD) is static phase offset or reset path delay. The proposed structure decreases the jitter resulted from PFD by switching two PFDs. In this new architecture, a conventional PFD is used before locking of DLL to decrease the amount of phase difference between input and output of DLL. Near locking an XOR gate is employed to act as a PFD which make the DLL lock with fewer jitter. Also, by using XOR gate the reset path time and glitch will be decreased. In addition, the proposed architecture is designed in TSMC 0.18um CMOS Technology. The simulation results support the theoretical predictions.